Definition

pipeline burst cache

A pipeline burst cache is a cache or storage area for a computer processor that is designed to be read from or written to in a pipelining succession of four data transfers (or bursts) in which later bursts can start to flow or transfer before the first burst has arrived at the processor. A pipeline burst cache is often used for the static RAM (static random access memory) that serves as the L1 and L2 cache in a computer. It was introduced in 1996 with Intel's Pentium series of processors. A pipeline burst cache is an alternative to an asynchronous cache or a synchronous burst cache.

In most personal computer processors, data is transferred along a path (or bus) that is 64 bits (8 bytes) wide. Since each line of storage in a cache is 32 bytes long, it takes four successive transfers to transfer the storage line. With a pipeline burst cache, the first transfer takes 3 of the processor's clock speed cycles, and the remaining three transfers take only one cycle each (since no time is required to locate the storage location for the remaining transfers). The adjectives pipelining and burst describe the idea that once the storage location has been addressed and accessed and the first read or write transfer is started, the subsequent transfers come rapidly in discrete bursts down (or up) the pipe or data path. The timing for the total transfer of a storage line using pipeline burst cache is usually shown as "3-1-1-1" or a total of 6 clock cycles.

This was last updated in April 2005
Posted by: Margaret Rouse

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