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Flash Memory Technologies and Costs Through 2025

You will learn how flash memory technology and design changes are dramatically shifting who the cost leaders are and some of the challenges in the market.

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00:11 Mark Webb: Hi, I'm Mark Webb and I'm from MKW Ventures Consulting, and I'll be talking about flash memory technologies and cost through 2025. Some of the contents we'll talk about today are NAND companies and current status; next-generation technologies and announcements that have been made and some speculation of what might happen in the future; model for cost reduction on NAND technologies going forward; relative die costs for all the current manufacturers on all the current chips they're shipping and what we project for the future; future bit costs through 2025; and then an ASP versus bit cost model and some of the challenges there.

00:56 MW: So, NAND companies and their current status. So, the 96-layer generation, which is 92 to 96 active layers, is a dominant technology today. It's ideal for 512 gigabit, it works for 256 gigabit and it's capable of 1 terabit plus. And one of the key things here is that we don't need new amounts of layers in order to get a higher density, that's not the push right now. The 96-layer is greater than 50% of the bit shipped today. The 128-layer generation, which will be 112 through 144 active layers, is being introduced now. It's going to be less than 15% of the bits in Q4 2020, so while it's been announced by many people, there's lots of comments on it, there'll be comments at this conference, that's still going to be a pretty minor bit contributor at the end of this year.

01:49 MW: One hundred and seventy-six-layer generation, which is 160 to 192 actual layers, is being announced and developed. And then a 256-layer generation is possible by all companies with no limit. So, we'll keep adding more layers and there's no current limit seen. Note, again, we're doing new technologies for lower cost, not capacity, and that'll be important when I talk about my cost slides.

02:14 MW: So, company updates. Samsung is moving to 128-layer now, it's still one string stack. This is actually quite amazing. Everybody else has gone to dual-string stack, but Samsung has been able to stick with one string on there, so there's no . . . It's all done at 1 inch and one contact call. No CMOS under the array, yet it is shipping, so this is important because this is something that they'll implement in the future, but right now it's not being implemented, and it does provide over probably about a 15% die size savings. SK Hynix is moving to 128-layer, two-string stack; it's CMOS under the array, they call it PUC, periphery under cell. WDC and Kioxia are running a 112-layer, two-string stack. We do expect at least some of the products will have CMOS under the array. Micron is in a very different position; they're doing a limited ramp or they've announced a limited ramp on 128-layer, two-string stack, CMOS under the array on the first generation replacement gate.

03:24 MW: Replacement gate means charge-trap technology in Micron's case. Micron previously had been running floating gate, they're moving to charge-trap flash now, like most of the competition is, and as a result of this we expect to see minimal cost reduction expected over 96-layer in the 2020 and 2021 time frame. And this is simply because they're ramping new technology, new tools, they have a lot of conversion costs, so it's going to really kind of hold them back. Intel is moving to 144-layer, floating gate, CMOS under the array, and I'm guessing here that it's a three-string stack. Look to TechInsights to provide data on what they see in their tear downs. So, this is where the companies are today.

04:11 MW: There's another company I didn't mention, which is YMTC in China. They've been making a lot of announcements for many years at this conference and other conferences. YMTC is now shipping 64-layer wafer-bonded, Xtacking technology. They plan to move to 128-layer -- I believe they made an announcement around February – but, in general, they tend to pre-announce things so I wouldn't expect it to be ramping any time soon because 64-layers is just ramping now. Sixty-four-layer product has excellent die size due to the CMOS under the array provided by wafer stacking, so by doing that, they do periphery on one wafer, they do the array on another wafer, they stack them, so you end up with a very small die size, stacked die size.

04:56 MW: The problem with this is this technology is very expensive and very complex. It's seen as a way to allow periphery to be optimized, but it is not cost competitive yet. Our model shows that the costs are 50% higher than competition, and that's if they hit their yield targets and get to maturity. YMTC is still less than 2% of the industry bit shipped annually, and if they execute to plan, we estimate that they could grow to over 5% market share by 2025. So, again, the key from last year is they are actually shipping some of these products, they have shown up in tear downs; however, the technology is very complex and we'll see if they're able to go scale this to 128-layers. Future technologies, all companies have announced moves to 1YY, which I guess I'll call 176, in late 2021. And then 2XX, which would be like a 256-layer technologies are possible. With Intel's announcements of the SK Hynix sell off, we expect floating gate to end, although a recent announcement by SK Hynix said that they would continue to run floating gate for another two to three generations, and this is primarily because Intel will be transferring the R&D from Intel to SK Hynix, so as a result they already have some work that's in progress.

06:16 MW: One other thing that I'd note, this came from IEDM papers last year, is a number of companies have actually experimented with floating gate for alternative architectures, but currently the only ones still using it as of today is Intel. The 176-layer nomenclature's being used for the next generation. We expect companies to make a pragmatic decision on the number of layers based on yields and costs, we've already seen this with 128 layer. So, an example is if you can make, say, a 160-layer technology cheaper or higher yield or avoid issues than 176, you might choose that. If you think you're going to install tools and be able to get to 182, you might do that, you're going to make a pragmatic decision, there's no set number that they have to go with. With a one- to two-year cadence - I'm assuming about 18 months normal -- we expect companies to convert some but not all of their nan products onto each new generation.

07:14 MW: QLC models. So, I was not really originally a fan of QLC back in 2017, but it appears that the MLC/TLC history will repeat itself on QLC. It'll start as a little bit cheaper with worse performance and endurance. We'll see few adoptions, lots of complaints, performance cache and controllers will improve the product, customers will become more tolerant of the issues, and it'll become dominant in bits over a seven- to eight-year timeframe. We model that QLC bits are around 15% in 2021, and they'll grow to 50% of bits after 2025. It's theoretically 25% cheaper, actual in our model is 20% to 23% cheaper after accounting for some design and test overhead costs. PLC, penta-level cell, is possible and we could expect the same timeline if that came out. So, again, if somebody introduced it, they have a chip and then maybe eight years later it crosses over and becomes 50% of the bits.

08:16 MW: The MKW Ventures model for NAND cost reduction. So, going into . . . The numbers are going to show you is each generation; we assume that we're going to add about 30% to 50% more layers, the goal for each technology when those come out is to improve manufacturing efficiency, so the output tool is the same, and the fab and tool vendors partner on this.

08:34 MW: So, as a result, the goal is to have no cost matter for adding all those layers. In reality, we've added 10% to 15% to wafer cost from each new generation, depending on inputs from tool vendors -- we talked to tool vendors about what's possible, what the tool costs are and get input that way. String stacking adds to the wafer cost, maybe 5% to 10%, seem awesome to the reads to wait for cost because you have to do some complexity in building that. And again, that might be another 5% to 10%. I'm sure technologies, however, we assume 5% to 10% cost improvement per year, so if I just took a given technology, I give it to a fab each year, they're going to reduce the cost 5% to 10% just on way for cost through efficiency improvements.

One change this year based on inputs from tool companies and from man companies, we significantly increase the way for cost improvement rate on three demand technologies, the end result is 3D and is becoming efficient and a faster rate than previously estimated. As a result, our cost improvements are improving in the model that I'm presenting, so here's a complex data. You can look at this offline, but basically this is named diecast doesn't include assembly test cost for TCR, QLC man technologies, A through year nan suppliers.

09:52 MW: I don't give the names here, we can talk offline about what the names are and what the differences are between companies, and then shows the cost for 2020, 2021 and 2022. And the key takeaways here on each given technology, the cost go down every year as you get more efficient. In some cases, if it's a mature, you still get some cost improvement just from ongoing learning. If it's a new technology like 128 layer this year, you're going to see a big jump in the first year and cost improvement because you get lower way for cost, improve yields and things like that. And then you can see that the next technology is 176 layer, and ultimately 256 layer -- they're going to continue to deliver a cost reduction. So, right now, adding layers always reduces the overall bit cost going forward. Again, this is actually translated to bit cost -- they said diecast, but it's actually bits for demand -- and the key takeaway is bits keep getting cheaper.

Now, I mentioned before that YMTC is doing a 64-layer technology based on X stacking.  If you look at this result, this is where I modeled the cost for in 2021 for YMTC 64-layer stacking technology, and the keys has a very small die size and this is assuming mature yields, but the wafer cost and the processing cost is much higher.

11:17 MW: And so, as a result, they're really not competitive on cost. So, what are the key takeaways from this? Costs are being reduced every year and with every new technology, we have exact numbers, company names and reasons for numbers available for follow-up discussions. I don't want to get all the details here. Each company has a different cost production path, and so each company will have either that are leaning faster, they're behind one interesting example here is that the cost leader at 96 layer is not the cost leader at 128 layer. In fact, their modeled to have their highest cost at 12 layer, so the companies who's leading in cost and who is trailing and cost changes each generation.

12:02 MW: And then the other one is we have line of sight to at least do 56 layers and we will keep getting cost reduction going there. I look at average cost trends for the next five years through 2025, I'm showing HDD cost and NAND cost. This is big cost, and this actually includes assembly and test cost for the technology, the end result is going to be named average costs will be below two cents per gigabyte after 2025. The cost reduction on hand is 20% per year on average, this includes what we get from new technologies, plus what we get from cost learning as fab has become more mature and equipment gets more efficient, plus it includes the effect of TLC percentage, which as I mentioned, is going to ramp from about 15% to 50% over the next five years, NAND and HDD crossover sometime after 2033.

13:00 MW: If you look at this on a log plot, you can see this, and then the updates, there was a presentation from a planned, they're going to replace nearline HDDs. If we had 100% Penta-Level Cell and it was yielding at forecast, the crossover would only move into 2031, so again, nearline HDDs are going to be around for a long, long time, and they will be the dominant for the low-cost storage. And, again, on this one, there's lots of data, you can contact me for numbers and log plots and things like that to make it clear, but again, it shows you what we're seeing a NAND cost again, not ASP versus HDD cost over the next five years.

13:42 MW: So, the name market as a market, pricing recovered some in early 2020, but then since struggled right now, nanograms are minimal, bit growth is unclear, but probably around 30% CAGR each year, and then the bit cost will drop 20% per year on average. As I mentioned, all these numbers add up to a very challenging financial model if prices dropped greater than 20% per year, historically, my model is you should focus on 20% to 25% price reduction per year. If we end up in this situation, the result would be a slowdown in new technologies and Capex because companies would have to decide how fast they want to invest and how fast they want to ramp new technologies.

14:31 MW: So, in summary, there's no end in sight for NA in technology progression and cost reduction. There's no major limiters to adding more layers, you will see improves cost and will grow to 50% of bids after 2025, NAND costs will each two cents per gigabyte after 2-25 also the name cost, leaders change over the next five years, and then costs are modeled across HDD cost after about 20, 33, if you include all technologies combined. Again, numbers back up, charge company names and reasons for numbers are all available calls to discuss, and additional contact information is shown here. Thank you.

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