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The future of flash memory promises unprecedented speed, capacity

NAND flash's future involves more layers and bits per cell. At the same time, NVMe-oF, storage class memory and other new technologies will fundamentally change memory and storage.

Predicting the future of any technology is never straightforward, and memory technologies are no different. Yet, when it comes to NAND flash, storage class memory and NVMe-oF, the possibilities are wide open.

In recent years, these technologies have evolved at a remarkable pace, with vendors producing faster devices that store more data and offer greater endurance. That's not to say there won't be snags along the way, but the future of flash memory and other related technologies is as promising as ever.

The future of 3D NAND

Many analysts believe vendors will keep adding layers to 3D NAND flash until it's no longer feasible. Already, 192-layer 3D NAND is expected by 2021 and 256-layer devices by 2022. Gregory Wong, president and principal analyst at Forward Insights, said he expects vendors will continue to increase the number of layers, as well as bit densities, while reducing overall costs. However, "adding layers requires ever-increasing Capex, higher process complexity and longer processing times," he said.

Tom Coughlin, president of Coughlin Associates, agreed that the number of layers will continue to increase, with devices using thinner layers and layer string techniques. But there are limits to how thin these layers can get and how fast depositions can be made. "Increasing the number of layers will result in longer wafer production time and the need for additional wafer capital equipment and, eventually, new factory production," he said.

Because of the production issues, the rate at which 3D NAND can continue to reduce the cost per GB will decline without additional technological advances, most notably the ability to use multiple bits per cell, Coughlin said. However, more bits per cell leads to slower performance because more error correction is needed, and it also decreases cell endurance. To be successful, "conventional garbage collection will need to be changed and, in particular, erase/write cycles must be reduced," he said, which will require using methods such as caching write data.

In the long run, memory and processing could come together to create true in-memory processing.
Tom CoughlinPresident, Coughlin Associates

The future of QLC and PLC NAND

NAND flash's future inevitably revolves around the number of bits per cell. Over the past year, the use of quad-level cell (QLC) NAND, with four bits per cell, has focused primarily on PCs, but that's about to change, Wong said. "This year, we expect to see QLC drives for storage in hyperscale data centers and its introduction into enterprise storage systems." This certainly seems to be the case. More vendors than ever are talking about working on or producing QLC devices.

However, Wong said, it's becoming more difficult to scale bit density and reduce costs in flash devices. "Nevertheless, NAND flash memory will be around for a long time, as there's no technology on the horizon that can compete on a bit-density and cost basis."

J Metz, a member of the Storage Networking Industry Association (SNIA) board of directors, has another take on QLC and the next generation of NAND flash, penta-level cell (PLC), with five bits per cell. Although he views these technologies as inevitable, he questioned how the market will bear them. With prices for triple-layer cell (TLC) devices dropping, it's uncertain whether the economics of one form will squeeze out the other.

"The question isn't whether or not there will be a use case for one-off memory devices (which is what PLC would ultimately be), but whether or not those same use cases -- for the same resources of production -- could be satisfied by existing technology."

Despite these concerns, there's plenty of momentum around QLC with new products coming out regularly. "Something cool about 3D NAND is that it has kept the cell size and capacitance about the same over several generations, and that has supported the development of good QLC," said Jim Handy, general director at Objective Analysis. He also believes this will likely be the case with PLC.

Even so, the future of flash memory will likely see more bits per cell continue to impact endurance. And that's why QLC NAND in the enterprise will likely be limited to read-intensive workloads, with write operations carefully controlled. This will be even truer for PLC NAND.

However, QLC and PLC NAND could be paired with single-bit cell (SLC) flash to create hybrid SSDs, Coughlin said. "Zone memory ideas may help in creating multiple flash technologies that could be used to concentrate writing in SLC flash and reading from QLC or even PLC flash," he said. The consensus is that QLC and PLC NAND aren't likely to be used on their own for high-performance applications.

Future of flash memory

The future of NVMe-oF

As more NVMe SSDs find their way into the data center, the push to incorporate NVMe-oF into enterprise workflows is projected to grow exponentially. The interface protocol extends the performance and low-latency benefits of NVMe across the network. Already, we're seeing evidence of the NVMe-oF trajectory in products such as Dell EMC PowerMax, which supports NVMe-oF to deliver lower latencies and faster response times for resource-intensive applications. Handy said he believes NVMe-oF is likely to become a standard system architecture that will enable flash use to rapidly grow.

Coughlin went further, predicting that NVMe-oF will become the dominate network storage technology, "particularly for primary storage applications, but perhaps even with HDD-based storage down the road." Western Digital already includes an HDD storage box in its OpenFlex architecture, which includes an NVMe-oF interconnect. If done right, NVMe-oF can provide network storage performance close to the internal bandwidth of the NVMe storage device, Coughlin said. NVMe-oF also makes it possible to use remote memory, creating "new virtualization and abstraction approaches," he added.

Metz is convinced that NVMe-oF opens a world of possible deployment options that, until now, have been out of reach. Advancements in the protocol make it possible to connect into the media with greater precision and granularity. Zoned Namespaces, a technology designed to precisely write data to media in efficient and performant ways, is perfect for media such as QLC and PLC, which are highly sensitive to overwrites and write cycles, Metz said.

Storage class memory and other emerging tech

With the release of Intel's DC Persistent Memory, the future of storage class memory (SCM) as a tier in the memory-storage hierarchy became more promising than ever. SCM will play an instrumental role in creating this new tier, in part, because it can reduce the amount of latency in situations where data can be at risk before being committed to memory, Metz said.

Metz also pointed to SNIA's Persistent Memory programming model, which offers "numerous extensions for applications that wish to address the media in block or file modes, as well as using the same media types for I/O or load/store semantics." This provides remarkable opportunities for application developers who wish to address the device directly, he said.

According to Handy, SCM can bring a new tier to the memory-storage hierarchy. He asserts that the future of SCM is limited only by "the amount of money Intel is willing to sink into creating the market." The company is likely losing billions of dollars a year on this venture, Handy said, but added he believes Intel will make it back in sales of higher-price processors. "No other vendor could justify taking this step," he said.

Storage-memory hierarchy

But the SCM movement isn't limited to Intel's Persistent Memory modules. Several embedded chip foundries offer SCM-type devices based on technologies such as magnetoresistive RAM (MRAM) and resistive RAM (RRAM), in addition to other emerging memory, Coughlin said.

According to Coughlin, MRAM will get faster as it moves from spin tunnel torque to spin orbit torque technology. "With such advances and with the smaller size of MRAM, we see it eventually replacing processor lower-level cache and, potentially, even replacing registers with non-volatile memory. Consequently, all memory could become non-volatile memory, which could have enormous implications for the design, security and programming of future electronics," he said.

Looking to the future of flash memory

Flash will continue to serve as the layer between HDD and memory channel tiers, even after storage class memory becomes mainstream, Handy said. "Persistent memory will do more to displace dynamic RAM (DRAM) than NAND flash, similar to the way that NAND SSDs have reduced the growth of DRAM in data centers," he said. At the same time, storage technologies such as NVMe-oF and software-defined storage will be more widely adopted, squeezing more productivity out of fewer resources, he added.

Non-volatile solid-state memory is undergoing a rapid evolution that will fundamentally change how we carry out computing. These changes will enable lower-power devices for edge and endpoint applications such as 5G IoT, particularly energy-constrained applications that rely on batteries or solar cells, Coughlin said. Technologies such as magnetoresistive RAM could get as cheap as DRAM and eventually replace it, he added. "In the long run, memory and processing could come together to create true in-memory processing."

By all accounts, the future of flash memory and other emerging memory technologies remains as promising as ever. According to Metz, we're at the beginning of a "Cambrian explosion of use cases" for solid-state memory, moving from a singular method of addressing flash to a "radically flexible and modifiable process of accessing information when you need it." With the work being done on bit densities, the protocols that access flash devices and the momentum in areas such as computational storage, "we are only beginning to see the possibilities."

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