TLC flash (triple-level cell flash) is a type of NAND flash memory that stores three bits of data per cell. TLC is also known as MLC-3, 3-bit MLC and X3.Content Continues Below
Common use cases for TLC flash include enterprise- and consumer-grade solid-state drives (SSDs), storage cards in digital cameras and mobile phones, and USB drives. TLC flash offers a lower price per gigabyte (GB) than single-level cell (SLC) and multi-level cell (MLC) flash, which typically stores two bits of data per cell.
NAND flash manufacturers commonly use TLC with 3D NAND flash, in which the memory cells are stacked vertically on the chip. The memory industry moved to 3D NAND flash, as manufacturers reached the scaling limits of two-dimensional (2D) or planar technology, which uses a single layer of memory cells. The 3D NAND enables higher storage densities at a lower cost per bit and improves the endurance of the flash. Samsung refers to its 3D NAND as V-NAND.
How does TLC NAND flash work?
NAND flash is a type of nonvolatile memory that can store a charge for an extended period of time whether or not a power supply is connected. NAND flash memory programs or writes bytes of data to a semiconductor chip only after an electronic charge has erased a unit of data known as a block, which can vary in size.
Each of the three bits of data in a TLC flash cell is either programmed (0) or erased (1). Based on the voltage level, a TLC memory cell has a total of eight possible states: 000, 001, 010, 011, 100, 101, 110 or 111. By contrast, SLC flash has only two states (0 or 1), and MLC flash has four states (00, 01, 10, 11).
Planar or 2D NAND flash typically uses a floating-gate transistor surrounded by an oxide insulation layer to store electrons and change the threshold voltage to program a cell to a zero or a one. The program/erase (P/E) cycle eventually erodes the oxide insulation layer, causing manufacturer-set threshold values to become distorted. The problem worsens with TLC over SLC or two-bit MLC planar NAND, because there are more values that can shift from the preset threshold points and cause errors.
SSD manufacturers generally use error-correction algorithms, overprovisioning, wear leveling and other mechanisms to improve the endurance and reliability of planar MLC and TLC NAND flash to enable its use across consumer and enterprise devices and flash storage systems.
Most TLC 3D NAND manufacturers have shifted away from the floating-gate approach to a charge-trap architecture that uses a silicon nitride film to hold the charged electrons. Potential advantages of the charge trap include lower cost and improved endurance and reliability. Because charge trap uses a lower voltage, the chances of defects and charge disturbances are reduced.
TLC vs. SLC and MLC
Two of the main advantages of TLC NAND flash over SLC and MLC are storage density and cost per bit. Because TLC flash stores more bits per cell, it can triple the capacity of SLC and offer 1.5 times more storage than two-bits-per-cell MLC. NAND manufacturers achieve the same capacity with a TLC die than they do with a 32 Gb MLC die by reducing the die size from 16 billion cells to 10.667 billion cells, enabling cost savings.
Drawbacks of TLC over SLC and MLC flash include performance, reliability and longevity.
The slower performance relates to TLC's eight voltage levels, in contrast to SLC's two levels of charge and two-bit MLC's four levels. TLC flash programs data more slowly because it requires more time to store the additional voltage levels. The voltage level must be checked and translated back to bits when reading data, and the translation process takes longer for TLC and its eight levels.
TLC NAND has a higher bit error rate than SLC and MLC flash, because the small difference between its eight voltage levels makes the read process more sensitive to noise. SLC has only one manufacturer-set threshold value at which a charge is determined to be a one or zero, whereas MLC has four and TLC has eight. Values can shift as the flash cell wears out, also leading to errors.
TLC flash has lower write endurance than both SLC and MLC flash. In general, the more bits of data and levels of charge that a planar NAND flash cell has, the fewer P/E cycles, or write cycles, it supports. SLC flash memory cells can withstand 50,000 to 100,000 P/E cycles before wearing out. A 2-bit planar MLC memory cell typically tolerates no more than 3,000 P/E cycles, and enterprise-grade MLC (eMLC) planar NAND has a limit of 10,000 P/E cycles. A planar TLC memory cell generally can sustain no more than 500 or 1,000 write cycles. However, with 3D NAND technology, the TLC size is larger, and it can approach the endurance level of planar floating-gate-based MLC flash.
With slower performance and lower endurance than SLC and MLC NAND, planar TLC flash originally saw use mostly in consumer devices, such as camera cards and USB drives. But the use of software-based error-correction and wear-leveling techniques enabled its use for read-intensive enterprise workloads. The use of 3D NAND with TLC flash has served to expand the enterprise use cases.