Definition

NAND flash wear-out

Contributor(s): Carol Sliwa
This definition is part of our Essential Guide: 3D NAND technology: What it is and where it's headed

NAND flash wear-out is the breakdown of the oxide layer within the floating-gate transistors of NAND flash memory. All of the bits in a NAND flash block must be erased before new data can be written. When the erase process is repeated, it eventually breaks down the oxide layer within the floating-gate transistors of the NAND flash.

The erase process involves hitting the flash cell with a relatively large charge of electrical energy. This causes the semiconductor layer on the chip itself to degrade a little, which over time can increase bit-error rates. At first, these errors can be corrected with software, but eventually the error correction code routines in the flash controller can't keep up with these errors and the flash cell becomes unreliable.

Endurance for a NAND flash drive is typically stated as total bytes written (TBW), which is a product of write cycles and the logical drive capacity. Endurance may also be expressed as the number of full drive writes per day, with one drive write being equal to the logical drive capacity.

Most enterprise-grade solid-state drives are designed to last between three and five years. The NAND flash wear-out figures that the industry typically cites are 100,000 program/erase (P/E) cycles for single-level cell (SLC) flash, 30,000 P/E cycles for enterprise multilevel cell (eMLC) flash and 10,000 or fewer P/E cycles for multilevel cell (MLC) flash.

This was last updated in January 2012

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