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NAND flash memory technologies evolve to support QLC

QLC NAND pushes the storage capacity of flash devices higher, but devices can wear out more quickly than other NAND types because more data can be written to the same cell.

Innovation around NAND flash memory technologies has centered on improving 3D NAND and increasing the number of...

bits that can be stored in each flash memory cell.

The 3D NAND technology -- sometimes referred to as V-NAND -- is designed to overcome flash memory capacity limitations and lower the cost per bit. The physical size of a memory cell limits the number of cells that can be placed onto a two-dimensional die, which also limits overall storage capacity. And 3D NAND flash memory overcomes these limitations by stacking memory cells in vertical layers, which increases storage capacity exponentially.

Early in the evolution of NAND flash memory technologies, the single-level cell (SLC) architecture was king. With SLC NAND, each memory cell can store 1 bit of information. Over time, storage vendors introduced the multilevel cell (MLC) and triple-level cell (TLC) NAND flash memory, which store 2 bits and 3 bits per cell, respectively. Quad-level cell (QLC) further increased storage capacity by allowing 4 bits of data to be stored within each cell.

QLC cons

Although QLC technology is relatively new, it significantly improves capacity, and it could be the last NAND architecture to do so by increasing the number of bits that a cell can store. That’s because there are several problems with increasing capacity this way.

The first problem is related to reliability. As bits are added to memory cells, it becomes increasingly difficult to ascertain their value. Over the course of multiple write cycles, the cells begin to degrade, making it more difficult to accurately read bit values. Error correction can help, but cells will eventually degrade to the point that reading the contents becomes impossible.

Another problem is that although increasing the bit count increases the overall capacity of the storage media, it also makes it slower. Consider the amount of time required to erase a cell for each of the NAND flash memory technologies: On an SLC drive, cell erasure takes around 1.5 to 2 milliseconds. The MLC architecture increases the erase time to 3 milliseconds. TLC cells have about a 5 millisecond cell erase time. And although no firm data exists for QLC, the erase time is estimated to be more than 6 milliseconds.

But the biggest problem with adding bits to cells is that doing so causes the cells to wear out more quickly. SLC drives can endure roughly 100,000 program/erase cycles. For MLC drives, that number plummets to about 3,000 cycles per cell. TLC drives only have about 1,000 write cycles per cell, and according to some estimates, a QLC drive may only be able to endure about 100 write cycles per cell.

The decreased durability of TLC and QLC NAND flash memory technologies might make them seem like they are best suited for use as high-performance archival systems. It might also seem like manufacturers would be able to create write-once-read-many flash storage by adding a few more bits to each cell. But the addition of bits has diminishing returns, even with regard to capacity.

MLC doubles SLC's capacity. TLC only increased capacity over MLC by about 33%. QLC achieves only a 25% capacity gain over TLC. The capacity gain would continue to decline with the addition of more bits.

The question remains: Why would anyone use a QLC drive if cells can only endure 100 write cycles? The short answer is that although cells fail after 100 write cycles, the entire drive does not fail as quickly. Storage vendors employ a number of tricks to extend the longevity of their QLC drives, including wear leveling and over provisioning.

In the future, storage vendors will likely find other techniques to improve the capacity of NAND flash memory technologies. In the short term, expect vendors to work to improve 3D NAND and increase the number of layers within storage architectures. Some vendors have begun experimenting with the stacking of logic components. By stacking these components, more space could be made available on the die for additional memory cells.

This was last published in March 2018

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