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Face-Off: EMC DMX-3 vs. Hitachi USP1100

Ezine

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Performance face-off
Users familiar with both systems in production environments say the arrays provide more than adequate levels of performance under the vast majority of operating environments. However, because EMC and HDS can hammer on each other's component-level architectural differences, they'll do so (see "Point, counterpoint," PDF at right). For example, HDS claims the DMX suffers from IO congestion because of a mixture of control and data transfers--an attack on EMC's point-to-point architecture. EMC counters that the USP suffers from significant latency issues because it needs to manage its separate control and data memory networks, indicting HDS' switch-based approach.

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Point, counterpoint
Click here for a Q&A on EMC DMX-3 vs. HitachiUSP1100 (PDF).

The reality is that a successful, high-scale, high-performance storage array can be built on either a switch-based or point-to-point-based architecture. Outside of a specific usage context, these are red herring technical arguments. Congestion and latency issues may or may not surface in the way memory is handled by the two architectures. Any competitive attacks that hark back to the controller or memory issues of the USP or DMX must be viewed in context of workload, deployment, memory optimization, connectivity and scale. Key words to listen for in a sales call are "congestion," "latency," "commingled" and "contention." Used in isolation, not in context, they're just words that indicate generic issues of an architectural approach, not a de facto limitation of the USP or DMX.

Capacity and scaling
The HDS pitch: A common approach to growing both internal and external capacities is the path to the highest possible scalability and flexibility, and USP is the only platform that can provide this. EMC doesn't even have a story for scaling outside the DMX itself.

The EMC pitch: The DMX-3 can scale to 1.1PB inside the array, and support the highest levels of flexibility for creating internal storage tiers at those scales. This saves money and management costs. Scaling the IO for production workloads outside of the array isn't a realistic option.

The real issue: Both arrays have demonstrated comparable internal scaling capabilities. The DMX-3 has higher absolute internal capacity, but the USP1100 can scale externally to support multipetabyte capacities. The question related to both arrays is, at what price-to-performance ratio are these numbers achieved?

This was first published in January 2007

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