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Face-Off: EMC DMX-3 vs. Hitachi USP1100

Ezine

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EMC approach
The DMX-3 sports a point-to-point Direct Matrix Architecture (see "EMC's Direct Matrix Architecture," at right), which enables very scalable performance. It's a critical element in the DMX story, but definitely not positioned as the crown jewel of the platform the way HDS touts its Universal Star Network architecture. The Direct Matrix connects all points between every front- and back-end director and their cache boards running on 1Gb/sec connections, not a crossbar switch like the USP. Because EMC scales performance in the DMX by providing direct point-to-point connections between every front- and back-end director and their cache boards, the company emphasizes that this architecture enables it to add more memory and capacity to support custom performance for different tiers. EMC leverages PowerPC chips rather than MIPS RISC processors.

One key EMC customer happily agrees that the DMX design works. "I can trust EMC's approach to scaling performance," says Vincent Hilly, managing director, data administration at Depository Trust & Clearing Corp. (DTCC), a financial services provider with a multihundred terabyte, multisite replicated environment.

This was first published in January 2007

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