Face-Off: EMC DMX-3 vs. Hitachi USP1100


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HDS approach
Without question, HDS places more emphasis on its controller architecture innovations than any other vendor in the market. As a result, any prospective customer evaluating HDS today must become comfortable with the company's explicit and unapologetic controller-centric view of enterprise storage intelligence, which is extremely different from the DMX-3.

At the core of the HDS USP1100 is the Hitachi Universal Star Network architecture, a massively parallel crossbar switch (see "USP1100 Universal Star Network," below). The key distinction of this controller, and one of the core design innovations enabling the entire HDS storage strategy, is that it creates two separate networks for control data and cache memory. There are actually four crossbar switches in the controller dedicated to providing nonblocking access to cache memory. In concert with this network, a smaller parallel network manages control data on a point-to-point network communicating between the MIPS RISC processors in the controller and the control memory. The crossbar multiplexes across 16 paths connecting the processors to the cache modules. This twin network of control data and cache plays a central role in far-ranging duties not just for the USP box, but for HDS' wider SAN strategy, including controller-based virtualization, heterogeneous replication and logical partitioning.

A range of algorithms are applied against this

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network controller architecture to provide cache optimization based on workload or dataset selection for permanent cache residency. The result of this extremely optimized architecture is the ability to transform the storage controller into a real-time, in-band IO platform for extremely large, mission-critical environments that's also capable of pervasive internal and external virtualization.

This was first published in January 2007

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