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This article is part of the Vol. 4 No. 1 March 2005 issue of Exploring the most innovative midrange systems
This article first appeared in "Storage" magazine in their March issue. For more articles of this type, please visit www.storagemagazine.com. At issue: Target-side TCP/IP Offload Engine chips have arrived, but the jury is still out on whether you should care. Last month, EMC announced a storage industry first: native iSCSI arrays that include target-side TCP/IP Offload Engine (TOE) chips on each front-end Gigabit Ethernet port. "We wanted to do it right," says Tom Joyce, vice president of storage platforms marketing at EMC, and bring iSCSI to "a class of customers that want to use IP to build a SAN -- not just kick the tires on the technology." Compared to earlier TOE-less EMC attempts at iSCSI -- the NS500 and NS700 -- these arrays deliver two to three times the performance, claims Joyce. But existing iSCSI vendors say EMC's use of TOE has more to do with the outdated processors powering the Clariion controllers than it does with luring iSCSI power users. While the Clariion controller uses a 1.6 GHz Intel Xeon processor, LeftHand Networks uses a 2.6 GHz ... Access >>>
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